Spy Interface

SystemVerilog
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Hi,

What is a spy interface in System Verilog? Is this similar as an interface?

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In reply to basilleaf:

This might be an informal term used by members of your team. I suspect it means an interface looking at internal signals of your DUT. You might want to read: Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy

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In reply to dave_59:

Thanks Dave for the resources