Interface direct connection at top level

SystemVerilog
,
1

What is the right sintax to connect interface signals as single at the top level?

I’ve created an example to ilustrate what i’d like to do that does not work.

Just at the top level of a module (exceptional case), I would like to be able to connect single interface lines as single:


.interfaz.b (driv)

but that does not work.
What would be the right syntax to do this?

Example code:


interface myitf (input bit b);
	byte a;
endinterface

module mymodule (myitf interfaz);
  initial begin
    interfaz.a = 7;
    $display("*** [info] my module interfaz.b = %b, interfaz.a = %d",interfaz.b, interfaz.a);
  end
endmodule

module mytb();
  // --- this works
  logic driv = 1'b1;
  myitf dummyitf(.b(driv));
  mymodule okmod (
    .interfaz (dummyitf)
  );
  // --- this does NOT work
  mymodule notokmod (
    .interfaz.b (driv)
  );
endmodule

Thank you for the help you can provide

2

In reply to stefaniemcg:

What you are asking cannot be done. This is an XY Problem.