How to connect unconstrained array of VHDL records to SV interface

SystemVerilog
, ,
1

Hello,
I have a DUT with an input port which id an array of unconstrained VHDL records. The record is defined in a VHDL package. It looks sth like this:
In the VHDL package:
Type myRecord is record
A : std_logic_vector(0 downto 0);
B : std_logic_vector(0 downto 0)
End record;
Type myArray is array(natural range<>) of myRecord;
In the VHDL DUT:
ENTITY myEntity is
Generic (num_of_ch : integer :=0);
Port(
Myport : in myArray(num_of_ch-1 downto 0);
…
I want to connect this VHDL module to a SV interface.
I compiled the VHDL package to be recognized also by thesv code.
What should be the type of the signal in the sv interface?

2

In reply to shaygueta:

There is no standard which dictates the interoperation of VHDL and SystemVerilog. As this is typically tool specific, you will need to refer to your tool documentation or contact your vendor support team for additional assistance.