Access internal signals wire/reg of DUT in interface

SystemVerilog
,
1

Can we access internal signals wire/reg in interface of SystemVerilog based layered testbench. For example, can we access msr and lsr internal signals of following code in interface?

module axi_uart_top #(parameter AXI4_ADDRESS_WIDTH = 5) (
    // Global signals
    input  wire s_axi_aclk, input  wire                          s_axi_aresetn,
    // write address channel
    input  wire                          s_axi_awvalid,
    output wire                          s_axi_awready,
    // UART Signals
    input 	wire			srx_pad_i);

wire	[7:0] msr;
wire	[7:0] lsr;
...
end module
2

In reply to yasirdv:

See Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy