Parameter type in interface

SystemVerilog
,
1

Hi All,

I have a question about systemverilog interfaces. I have a package that has a type defined. I am passing this type in as a parameter to an interface declaration. Now when I declare the interface and connect it to a port of a subblock (which is also of the same interface type) does the port automatically inherit the type parameter from the interface declaration? Showing some pseudo code below. Question is does the in port “in” in the subblock module inherit the datatype of “x” in interface.

interface #(parameter type some_type_t) myinterface;
some_type_t x;
// Modport definitions as well..not showing them

endinterface

module top (
);
      typedef logic [31: 0] d_t;
 
      my_interface #(.some_type_t(d_t)) mi();

      submodule dut ( .in (mi)  )


endmodule


module submodule (
          myinterface.slave in
);

endmodule
2

Correct, the parameterization gets passed on through the port. There is no way to specify that you want a particular parameterization to connect to the port.

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