Below is the snippet of my code
Module top:
module top_tb;
bit pclk;
always #5 pclk = ~pclk;
apb_intf apb_vif(pclk);
port_intf port_vif();
initial begin
pclk = 0;
end
top dt(/*signal connections to dut*/);
initial begin
uvm_config_db#(virtual apb_intf.m1)::set(null, "*", "vif1", apb_vif.m1);
uvm_config_db#(virtual apb_intf.m2)::set(null, "*", "vif2", apb_vif.m2);
uvm_config_db#(virtual port_intf)::set(null, "*", "vif", port_vif);
end
initial begin
run_test("my_test");
end
endmodule
apb_interface:
interface apb_intf(input logic pclk);
//signals
clocking block1 @(posedge pclk);
///signals for driver
endclocking
clocking block2 @(posedge pclk);
////signals for monitor
endclocking
modport m1(clocking block1);
modport m2(clocking block2);
endinterface
port_interface:
interface port_intf;
//signals
//no clocking blocks and modports used
endinterface
test:
class my_test extends uvm_test;
`uvm_component_utils(my_test)
function new(string name = "my_test", uvm_component parent = null);
super.new(name, parent);
endfunction
// sequence handle
env en;
env_config en_cfg;
apb_agent_config apb_agt_cfg;
port_agent_config port_agt_cfg;
function void build_phase (uvm_phase phase);
super.build_phase(phase);
en_cfg = env_config::type_id::create("en_cfg");
apb_agt_cfg = apb_agent_config::type_id::create("apb_agt_cfg");
port_agt_cfg = port_agent_config::type_id::create("port_agt_cfg");
if(!uvm_config_db #(virtual abp_intf.m1)::get( this, "", "vif1", apb_agt_cfg.vif1))
`uvm_error(get_type_name(),("cannot get virtual apb_intf.m1"));
if(!uvm_config_db #(virtual abp_intf.m2)::get( this, "", "vif2", apb_agt_cfg.vif2))
`uvm_error(get_type_name(),("cannot get virtual apb_intf.m2"));
if(!uvm_config_db #(virtual port_intf)::get( this, "", "vif", port_agt_cfg.vif))
`uvm_error(get_type_name(),("cannot get virtual port_intf"));
en_cfg.apb_agt_cfg = apb_agt_cfg;
en_cfg.port_agt_cfg = port_agt_cfg;
uvm_config_db #(env_config)::set( this, "*", "en_cfg", en_cfg);
en = env::type_id::create("en",this);
// seq creation
endfunction
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this, "RAL Test start");
//starting seq on seqr
phase.drop_objection(this, "RAL Test end");
endtask
endclass: my_test
apb_agent_config:
class apb_agent_config extends uvm_object;
`uvm_object_utils(apb_agent_config)
uvm_active_passive_enum active = UVM_ACTIVE;
virtual apb_intf.m1 vif1;
virtual abp_intf.m2 vif2;
function new( string name = "apb_agent_config" );
super.new(name);
endfunction
endclass
port_agent_config:
class port_agent_config extends uvm_object;
`uvm_object_utils(port_agent_config)
uvm_active_passive_enum active = UVM_ACTIVE;
virtual port_intf vif;
function new( string name = "port_agent_config" );
super.new(name);
endfunction
endclass
env_config:
class env_config extends uvm_object;
`uvm_object_utils(env_config)
function new(string name = "env_config");
super.new(name);
endfunction
//switches
apb_agent_config apb_agt_cfg;
port_agent_config port_agt_cfg;
endclass
env:
class env extends uvm_env;
`uvm_component_utils(env)
apb_agent apb_agt;
port_agent port_agt;
env_config en_cfg;
// other component handles
function new(string name="env",uvm_component parent=null);
super.new(name,parent);
endfunction
// BUILD PHASE
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db #(env_config)::get(this,"","en_cfg", en_cfg))
`uvm_fatal(get_type_name(),("cannot get virtual en_cfg"));
uvm_config_db#(apb_agent_config)::set( this, "*", "apb_agt_cfg", en_cfg.apb_agt_cfg);
apb_agt = apb_agent::type_id::create("apb_agt",this);
uvm_config_db#(port_agent_config)::set( this, "*", "port_agt_cfg", en_cfg.port_agt_cfg);
port_agt = port_agent::type_id::create("port_agt",this);
//other component creations
endfunction
////CONNECT PHASE
function void connect_phase(uvm_phase phase);
// connections
endfunction
endclass
apb_driver:
class apb_driver extends uvm_driver#(apb_seq_item);
`uvm_component_utils(apb_driver)
virtual apb_intf.m1 vif;
apb_agent_config apb_agt_cfg;
function new(string name="apb_driver",uvm_component parent=null);
super.new(name,parent);
endfunction
// BUILD PHASE
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(apb_agent_config)::get(this, "", "apb_agt_cfg", apb_agt_cfg))
`uvm_fatal(get_type_name(),("cannot get apb_agt_cfg"));
endfunction
// CONNECT PHASE
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
vif = apb_agt_cfg.vif1;
endfunction
// RUN PHASE
task run_phase(uvm_phase phase);
super.run_phase(phase);
//driving
endtask
endclass
apb_monitor:
class apb_monitor extends uvm_monitor;
`uvm_component_utils(apb_monitor)
//seq item handle
//port
virtual apb_intf.m2 vif;
apb_agent_config apb_agt_cfg;
function new(string name = "apb_monitor", uvm_component parent = null);
super.new(name, parent);
endfunction
// BUILD PHASE
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(apb_agent_config)::get(this, "", "apb_agt_cfg", apb_agt_cfg))
`uvm_fatal(get_type_name(),("cannot get apb_agt_cfg"));
///..
endfunction
// CONNECT PHASE
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
vif = apb_agt_cfg.vif2;
endfunction
// RUN_PHASE
task run_phase(uvm_phase phase);
super.run_phase(phase);
//capture
endtask
endclass
similar for port_driver and monitor. only difference is I am getting the apb_intf in port driver and monitor to use its clock.
I am getting the following errors and warnings:
WARNING VCP2515 “Undefined module: abp_intf was used. Port connection rules will not be checked at such instantiations.” “apb_agent_config.sv” 7 28
WARNING VCP2515 “Undefined module: abp_intf.abp_intf.m2 was used. Port connection rules will not be checked at such instantiations.” “apb_agent_config.sv” 7 28
WARNING VCP2515 “Undefined module: abp_intf.abp_intf.m1 was used. Port connection rules will not be checked at such instantiations.” “test.sv” 27 45
ERROR VCP2852 “Incompatible types at assignment: .apbvif ← this.apb_agt_cfg.vif2.” “port_monitor.sv” 33 31
ERROR VCP2852 “Incompatible types at assignment: .vif ← this.apb_agt_cfg.vif2.” “apb_monitor.sv” 27 27
I am not able debugg this. please help!