How and where to connect bi-directional signal?
interface sram_if # (parameter ADDR_WIDTH =10,DATA_WIDTH =32, STRB_WIDTH = DATA_WIDTH/8) (input bit clk );
logic rst;
logic en;
logic we;
logic [ADDR_WIDTH-1:0] addr;
logic [DATA_WIDTH-1:0] data;//bi directional
logic [STRB_WIDTH-1:0] strb;
logic region;
endinterface
module top;
import uvm_pkg::*;
`include "uvm_macros.svh"
import sram_pkg::*;
logic clk;
logic rstn;
initial begin
clk = 0;
forever begin
#10 clk = ~clk;
end
end
initial begin
rstn = 0;
repeat (5) @ (posedge clk);
rstn = 1;
end
//CONNECT interface ports
sram_if intf(clk );
sram #(
.ADDR_WIDTH(`ADDR_WIDTH),
.DATA_WIDTH(`DATA_WIDTH)
) dut (
.clk (clk),
.rstn (intf.rst),
.en (intf.en),
.we (intf.we),
.addr (intf.addr),
.data (intf.data),
.strb (intf.strb),
.region (intf.region)
);
initial begin
clk <= 0;
uvm_config_db#(virtual sram_if)::set(null,"*","sram_if",intf);
run_test ("sram_base_test"); //start test
end
endmodule