How use interface in verification of a module that has not use interface?

SystemVerilog
,
1

I want to do standard verification for a module.
It is not used interface in this module and it has a lot of inputs and outputs.
what is the best way to use the interface in the testbench?

2

You just break out the interface signals in the DUT instantiation

e.g. below the slave signals are connected to a Slave interface
and the master signals are ocnnected to a Master interface

switch DUT(.clk(clk),
.rst(rst),
.slv_din(SB_rhs_agent_bus.slv_din),
.slv_din_en(SB_rhs_agent_bus.slv_din_en),
.slv_dout(SB_rhs_agent_bus.slv_dout),
.slv_dout_en(SB_rhs_agent_bus.slv_dout_en),
.mstr_din(SB_lhs_agent_bus.mstr_din),
.mstr_din_en(SB_lhs_agent_bus.mstr_din_en),
.mstr_dout(SB_lhs_agent_bus.mstr_dout),
.mstr_dout_en(SB_lhs_agent_bus.mstr_dout_en)
);