Driving DUT internal signals with bind module


I’m trying to force internal DUT signals by a SV module. But signals are not driven.

module dut_bind#(string    agent_name = "",
                 string    if_instance_name = "vif")
  (input logic        clk,
   input logic        reset_n,
   input logic        valid,
   input logic [7:0]  data

  import uvm_pkg::*;

  vif vif_i (.clk(clk), .reset_n(reset_n));

  initial begin
    uvm_config_db#(virtual vif )::set(null, $sformatf("uvm_test_top.tb.%s", agent_name), if_instance_name, vif_i);
    force valid = vif_i.valid;
    force data  = vif_i.data;

    .clk    (ck_xgmii_x_a),
    .valid (internal_valid),
    .data (internal_data));

Is there any way to drive DUT signals using module ports?

In reply to alexkidd84:

It do not really understand what your intention is and why you are using agent and virtual interface as parameters. Finally you have only inputs and your bind module this does not allow to drive anything. You can drive only outputs.
The bind construct allows you to observe/drive any internal signal in your DUT.

In reply to alexkidd84:

You declared data and valid as inputs to dut_bind. You need to declare them as outputs and make sure they are wires on both sides of the port connection. Otherwise the force or not proper gate across the port boundary.

Also see: Replacing SV code in an RTL module with UVM bind | Verification Academy and interface registering by itself ? | Verification Academy