Replacing SV code in an RTL module with UVM bind

UVM
,
1

I have an RTL module …

module foo;

// RTL code
// .
// .
// .
// .

// Then there is some SV code to introduce errors 

`ifndef SYNTHESIS
error_module em_i0 ();

always @ (posedge some_event) begin
   force something;
   release something;
end

`endif

endmodule

How do I remove the SV code in this module and do the same thing using UVM bind?
Thank You!

2

If the something is a wire, you can do

module to_bind_in_another_module(output wire something, input some_event);
error_module em_i0 ();

always @ (posedge some_event) begin
  force something=1;
  release something;
end

endmodule

bind foo to_bind_in_another module bind_inst0(somesignalinfoo,anothersignalinfoo);

But this will not work if the signal is a variable.

3

In reply to dave_59:

My bad!
It isn’t a wire; it is of type reg.
reg [width-1:0] something;

Please advise. Thank You!

4

In reply to new_to_uvm:

This might work using an upward name hierarchical reference.

module to_bind_in_module_foo;
error_module em_i0 ();
 
always @ (posedge foo.some_event) begin
  force foo.something=1;
  release foo.something;
end
 
endmodule
 
bind foo to_bind_in_module_foo bind_inst0();
5

In reply to dave_59:

For reg[width-1:0] something,
I think ref port can be used.

module to_bind_in_another_module(ref reg[width-1:0] something, input some_event);
error_module em_i0 ();
 
always @ (posedge some_event) begin
  force something=1;
  release something;
end
 
endmodule