Replacing SV code in an RTL module with UVM bind

UVM
,
1

I have an RTL module …

module foo;

// RTL code
// .
// .
// .
// .

// Then there is some SV code to introduce errors 

`ifndef SYNTHESIS
error_module em_i0 ();

always @ (posedge some_event) begin
   force something;
   release something;
end

`endif

endmodule

How do I remove the SV code in this module and do the same thing using UVM bind?
Thank You!

2

If the something is a wire, you can do

module to_bind_in_another_module(output wire something, input some_event);
error_module em_i0 ();

always @ (posedge some_event) begin
  force something=1;
  release something;
end

endmodule

bind foo to_bind_in_another module bind_inst0(somesignalinfoo,anothersignalinfoo);

But this will not work if the signal is a variable.

3

In reply to dave_59:

My bad!
It isn’t a wire; it is of type reg.
reg [width-1:0] something;

Please advise. Thank You!

4

In reply to new_to_uvm:

This might work using an upward name hierarchical reference.

module to_bind_in_module_foo;
error_module em_i0 ();
 
always @ (posedge foo.some_event) begin
  force foo.something=1;
  release foo.something;
end
 
endmodule
 
bind foo to_bind_in_module_foo bind_inst0();
5

In reply to dave_59:

For reg[width-1:0] something,
I think ref port can be used.

module to_bind_in_another_module(ref reg[width-1:0] something, input some_event);
error_module em_i0 ();
 
always @ (posedge some_event) begin
  force something=1;
  release something;
end
 
endmodule
6

Hi dave_59,
The link to your paper in this thread seems to be broken. I was not able to download it or view it. Can you please post the link again? Many thanks!

We have some discussions in our team regarding the issue of forcing/reading a HDL signal from UVM benches. Does anyone have a good recommendation or coding guideline for this?

My impression is that it’s always not recommended to use hierarchal reference from SV class, but I’d like to hear your opinion on this.

Currently we have 3 methods for this:

(1) Keep the hierarchical reference in the top-level testbench, connect the signal to an interface, and pass the interface to the UVM testbench. Then a test sequence can drive/read that signal thru the virtual interface.

(2) Bind the interface to the module that has the signal we need to drive/read, and pass the interface to the UVM bench. Similar approach as dave_59 addressed in this thread.

(3) Use UVM tasks uvm_hdl_read/force tasks. This may not be recommended since there could be a tool dependent issue that extra switches may need to be specified to make it work properly for a simulator. Also, if the path string pass to the tasks are not correctly, errors may not be reported.

Please advise!

Thanks,
Richard

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