Replacing SV code in an RTL module with UVM bind

UVM
,
2

If the something is a wire, you can do

module to_bind_in_another_module(output wire something, input some_event);
error_module em_i0 ();

always @ (posedge some_event) begin
  force something=1;
  release something;
end

endmodule

bind foo to_bind_in_another module bind_inst0(somesignalinfoo,anothersignalinfoo);

But this will not work if the signal is a variable.