Whether using the UVM RAL or any other kind of home-brewed register model with a hierarchical backdoor reference into register map of a DUT, does using such a model violate the commonly understood verification principle of not being able to look inside the DUT (i.e. treat it as a black box)?
Thank you.
In reply to ce_2015:
Yes it does. But I have yet to be on a project where that ideal principle was followed to an extreme in the name of practicality. There are usually simple tests you can make to verify the accessability of your registers as a black box. Once verified, there is no need to burden all the rest of your tests with the front-door access overhead.