Topic	Replies	Views	Activity
Macro expansion with path name causes syntax error SystemVerilog SystemVerilog , modelsim , compilation-macro	2	1523	February 5, 2020
How to write Predictor Model in UVM structure? UVM UVM , Coverage , questa , modelsim , scoreboard-predictor-comparator	0	859	October 19, 2019
How to pass arguments from cmd to tcl script of ModelSim UVM UVM , modelsim , simulation-script , pass-argument-to-script	3	5022	March 22, 2017
Problem with DUT DDR input -> SDR output OVM OVM , Verification , modelsim , Xilinx , unisim , ddr	1	2289	March 11, 2016
Why do I get SIGSEGV Bad Handle or Reference error when p_sequencer.some_method() is invoked? UVM UVM , p_sequencer , modelsim , bad-handle-or-reference	1	5098	November 17, 2015
When is "Compiling package uvm_sv_unit" triggered in vlog compile? UVM UVM , compilation , modelsim , uvm_sv_unit , uvm-harness	4	2060	June 30, 2015
Running UVM example on MODELSIM - ALTERA 10.1d UVM UVM , System-Verilog , Verilog , modelsim , Altera	4	5209	March 18, 2015

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