Macro expansion with path name causes syntax error

SystemVerilog
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1

I’m having some trouble with a macro that is being passed on the command line to modelsim. The macro points to a relative path and populates an array for a compnent. The macro looks like:

+define+SKLIB_ALTERA_MIF_DIR="../../../products/jCIC/systemsim/../COM_LIB/sklib_altera_common/mif/"

and it is being used like so:

`ifdef SKLIB_ALTERA_MIF_DIR
        altera_syncram_component.init_file = {`SKLIB_ALTERA_MIF_DIR,"wiz_lgmt_ram_init.mif"},
`else

Now if I take that define and place it inside the file where it is being used there is no issue. However when I pass it in on the command line I get the following:

** Error: (vlog-13069) ** while parsing macro expansion: 'SKLIB_ALTERA_MIF_DIR' starting at ../../../products/jCIC/systemsim/../jcic/verilog/../../COM_LIB/sklib_altera_10AX/wiz_lgmt_ram/ram_1port_170/sim/wiz_lgmt_ram_ram_1port_170_jbudntq.v(75)
** at ../../../products/jCIC/systemsim/../jcic/verilog/../../COM_LIB/sklib_altera_10AX/wiz_lgmt_ram/ram_1port_170/sim/wiz_lgmt_ram_ram_1port_170_jbudntq.v(75): near ".": syntax error, unexpected '.'.

My theory is that for some reason when it is passed in on the command line the quotation marks are removed but I can’t figure out how to get them to persist when the macro is expanded.

2

In reply to cdjones42:

This is going to be a tool, shell, or scripting language issue. You are going to have to look at your tool’s manual or contact your tool vendor for support.

If you can use SystemVerilog, then you can avoid the quotes on the command line altogether and use a macro

+define+SKLIB_ALTERA_MIF_DIR=../../../products/jCIC/systemsim/../COM_LIB/sklib_altera_common/mif/

`define STRCONCAT(s1,s2) `"s1``s2`"
`ifdef SKLIB_ALTERA_MIF_DIR
  altera_syncram_component.init_file = `STRCONCAT(`SKLIB_ALTERA_MIF_DIR,wiz_lgmt_ram_init.mif)
`else
3

In reply to dave_59:

adding the STRCONCAT macro seems to have fixed it.