In reply to cdjones42:
This is going to be a tool, shell, or scripting language issue. You are going to have to look at your tool’s manual or contact your tool vendor for support.
If you can use SystemVerilog, then you can avoid the quotes on the command line altogether and use a macro
+define+SKLIB_ALTERA_MIF_DIR=../../../products/jCIC/systemsim/../COM_LIB/sklib_altera_common/mif/
`define STRCONCAT(s1,s2) `"s1``s2`"
`ifdef SKLIB_ALTERA_MIF_DIR
altera_syncram_component.init_file = `STRCONCAT(`SKLIB_ALTERA_MIF_DIR,wiz_lgmt_ram_init.mif)
`else