Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

UVM
, , , , ,
1

I am new to RAL and I am running the default uvm_reg_hw_reset_seq in my test. The test is failing for a register with non zero reset value. It is passing for others which have 0 as the reset value. I get an error as follows :
“m_ral_model.xxxx_REG” value read from DUT (0x0000000000000035) does not match mirrored value (0x00000000xxxx0000).

The mirrored value shows 0 instead of 'h35

I can see the read transaction on the bus, i.e. 'h35 being read on the bus but somehow I get the above error. Also in the generated ral model I can see the configured value for this register is correct ('h35)

I am also running uvm_reg_bit_bash_seq and uvm_reg_access_seq sequence which are passing and I can see the transactions on the bus.
What could be the possible reasons for this kind of mismatch only in case of reset seq ?

2

In reply to GC:

Did you do a reset on the RAL model prior to running the sequence?

3

In reply to chr_sue:

I already tried applying reset to the model in reset phase of my test but it did not work. I think the default uvm_reg_hw_reset_seq does that implicitly but I did try doing the following in my test but I still see the same error.

 task reset_phase(uvm_phase phase);
     xxx_env.m_ral_env.m_ral_model.reset();
 endtask : reset_phase

Is there anything else I can try to debug this issue ?

4

In reply to GC:

You should not use the sub_phases of the run_phase. Simply use the run_phase.
In the run_phase you have to execute the reset of the RAL model.

task run_phase(uvm_phase phase);
....
     xxx_env.m_ral_env.m_ral_model.reset();
// start the reset sequence.
...
 endtask : run_phase
5

In reply to chr_sue:
I just tried adding it right before starting the sequence as you suggested but it shows the same error.

In the reg model I see the reset value is configured correctly as follows :

 xxxx.configure(this, 16, 0, "RW", 0, 16'h0035, 1, 1, 1);

The waves also show the correct value, I am just confused why is it throwing the error about the mirrored and desired value mismatch.

6

In reply to GC:

Did you try to run a simple WR/RD to this register?

7

In reply to chr_sue:

I tried doing only a simple read from only this register after DUT reset in my test like the following

    p_sequencer.regmodel.get_reg_by_name(reg_name).read(status,read_data);

I print the read_data and it shows 'h35 without any error and waveforms also show it on the bus correctly.

After dut reset, I also tried using mirror function for only this register’s particular field with value 'h35 as reset value :

p_sequencer.regmodel.get_reg_by_name($sformatf("XXXXXX_REG")).get_field_by_name("XXXX_field").mirror( .status( status ), .check( UVM_CHECK ) );
     $display("mirrored data status is %s",status);

I get status as UVM_IS_OK. Not sure why is it throwing an error while running the default seq uvm_reg_hw_reset_seq, what else can i check ?

8

In reply to GC:

Where can I check the implementation of the inbuilt uvm ral sequences like uvm_reg_hw_reset_seq ?
I don’t understand what has gone wrong here.
The error comes as follows so I think I might need to check uvm-1.1d implementation of these sequences, where can I get this code ?

UVM_ERROR verilog_src/uvm-1.1d/src/reg/uvm_reg.svh(2889) @ 345000: reporter [RegModel] Register "m_ral_model.xxxxx_REG" value read from DUT (0x0000000000000035) does not match mirrored value (0x00000000xxxx0000)
9

In reply to GC:

It’s a little bit curious. But you do not print out the read value. Ypou are printing the status only.
I do not know how big your code is, but is it possible to share your code personally with me?
I’d spend some time to investigate your problem.
You can reach me here
christoph@christoph-suehnel.de