Verification Academy
Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test
UVM
uvm_reg_hw_reset_seq
,
RAL-UVM
,
RAL-UVM-PREDICTOR
,
Mismatch-in-read-and-mirrored-value
,
UVM
,
Systemverilog-UVM-RAL
chr_sue
November 19, 2023, 10:20am
2
In reply to
GC
:
Did you do a reset on the RAL model prior to running the sequence?
show post in topic