Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

UVM
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4

In reply to GC:

You should not use the sub_phases of the run_phase. Simply use the run_phase.
In the run_phase you have to execute the reset of the RAL model.

task run_phase(uvm_phase phase);
....
     xxx_env.m_ral_env.m_ral_model.reset();
// start the reset sequence.
...
 endtask : run_phase