Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

UVM
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3

In reply to chr_sue:

I already tried applying reset to the model in reset phase of my test but it did not work. I think the default uvm_reg_hw_reset_seq does that implicitly but I did try doing the following in my test but I still see the same error.

 task reset_phase(uvm_phase phase);
     xxx_env.m_ral_env.m_ral_model.reset();
 endtask : reset_phase

Is there anything else I can try to debug this issue ?