Verification Academy
Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test
UVM
uvm_reg_hw_reset_seq
,
RAL-UVM
,
RAL-UVM-PREDICTOR
,
Mismatch-in-read-and-mirrored-value
,
UVM
,
Systemverilog-UVM-RAL
chr_sue
November 20, 2023, 7:37am
6
In reply to
GC
:
Did you try to run a simple WR/RD to this register?
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