Ral Model with multiple instance of same reg block with restriction on port accessing

UVM
,
1

Is it POSSIBLE to maintain a single RAL model, When the identical instances of reg blocks have a restriction on which interface port can access them?
say instances 0,1 are accessed through an interface port and instances 2,3 are accessed through another interface port.
This validation is at the subsystem level, a higher-level switch controls these 2 ports in SoC.

2

In reply to ssubramani:

The question is not through how many interfaces you can access a register model, it is which kind of interfaces you are using.