Read only regsiter access using RAL

UVM
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1

My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write ?

2

In reply to dddvlsique:
Generally, there are two types of RO registers.

  1. Capability register: Set initially (while generating RDL/RAL) saying the capability of design
  2. Status register: Only design can update it. For TB it’s RO.

To verify Capability register:

  1. Unmask the RO register to write
  2. Write with any value other than default
  3. Read this register. It should return the default value only

To verify Status register:

  1. Read the register and store the value
  2. Unmask the RO register to write
  3. Write with any value other than previously read (you can use invert value)
  4. Read this register again and compare it with previously read value