Variable type is not user defined type

UVM
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1

For below code snippet seeing compilation issue saying variable type is not user defined type

Error-[SE] Syntax error
Following verilog source has syntax error :
variable type is not user defined type
path_to_error.env.svh
token is ‘Reg_h’
rand reg1 Reg_h;

file name: reg_file.svh

class reg1 extends base_reg
//other tasks//
endclass

file name: env.svh
`include "reg_file.svh"
class env extends base_env
rand reg1 Reg_h;
//some tasks//
endclass

package pkg;
`include "env.svh"
endpackage
2

In reply to Swetha E:

Where is class reg1 defined? It probably needs to be in a package that gets imported into pkg.

See SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

3

class reg1 is defined inside file reg_file.svh which is included in env.svh.
And file reg_file.svh is getting compiled. But the class reg1 inside reg_file.svh is not able to find it.

4

In reply to Swetha E:

The code you have shown is missing semicolons, but there are probably other problems with the code you have not shown.

5

In reply to dave_59:

Start with these simple guidelines. They may not

  • Put every class in a separate file, like reg1.svh and env.svh
  • Include each of these in a package, grouping together all definitions for a single protocol, such as axi_pkg.sv
  • Start the package with importing the UVM package and macros
  • Don’t include files / classes anywhere else
  • Compile the package
  • Import the package in other packages, or into your top test module with: import axi_pkg::*;

These won’t solve all issues, but they do help you get organized.