Uvm ral - explicit prediction

UVM
1

Hi,

Can anyone give an example of ral explicit prediction for atleast a single register write/read.

Thanks.

2
  1. Generate reg data/reg transaction
  2. Adapter
    Convert reg-tx to bus-tx
  3. Sent to driver
  4. Driver apply stimuli to DUT
  5. Driver collect response of transaction
    Send it to sequencer
  6. Reg model use that response to update Desired and Mirror value.
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1 Like
3

Thank you so much. I understood the overview of the same.
If you dont mind could you share the skeleton code/ Template of the same for the uvm_reg_predictor class & connections in the env.