NO_VIF: virtual interface must be set for:test.env.vif

Hi,
I am having a problem of getting in the interface using the right path in the environment. My testbench has instance of RxCxsCcb1. Thank you for your help.

My error
regr.attribute: failmsg = 0:F:test.env: NO_VIF: virtual interface must be set for:test.env.vif

My env


function void build_phase(uvm_phase phase);
super.build_phase(phase);
if_path = “pcie_iod_tb.RxCxsCcb1.m_cxsb_txrx.m_cxsb_txrx_if1.u_if”; //Check this path
if(!uvm_config_db#(virtual cxsb_txrx_full_if)::get(null , “”, if_path, vif))
`vvm_fatal(“NO_VIF”,{“virtual interface must be set for:”,
get_full_name(),“.vif”});

My tb

CxsCcb #( .NUM_ASYNC_FIFO_ENTRIES (8),
.NUM_CXS_RX_LCREDIT (4’d7)
) RxCxsCcb1 (

My bind file
bind RxCxsCcb1 cxsccb_if m_cxsb_txrx (.*);

My module get binded
module cxsccb_if (

cxsb_txrx_if m_cxsb_txrx_if1 (
.CLK (RXCLK),
.RESETn (~RXRESET),

In reply to nhatd2k:

Your get() call to the uvm_config_db seems incorrect.

I recommend reading the Verification Academy section on the UVM Configuration Database and fixing your get() call.