Triggering SV event as part of sequence expression

SystemVerilog
, , ,
1

I am trying the following code ::

module tb;
  bit clk , req , gnt ;
  event  evnt;
  always #5 clk = !clk;
  
  sequence seq;
    @(posedge clk) req ##1 gnt ##0 -> evnt ;  // Is this legal ?
  endsequence  
  
  cover property( seq );
    
  always@(evnt) $display("Event triggered at T:%0t",$time);
    
  initial begin  
    #14; req = 1;
    #10; gnt = 1;
    #2 $finish();
  end 
endmodule

I currently observe a compilation error for the event trigger.
I am aware that a boolean expression is legal as part of sequence_expression,
not sure on triggering an event as sequence_expression.

For now the following 2 alternatives work ::

  1. Trigger the event from pass action block
cover property( seq ) -> evnt;
  1. Trigger the event from subroutine
function void event_trigger();
 -> evnt;
endfunction

sequence seq;
   @(posedge clk) req ##1 ( gnt , event_trigger ) ; 
endsequence
2

The syntax allows

sequence_match_item ::=
    operator_assignment
    | inc_or_dec_expression
    | subroutine_call

But why create an extra event when you already have an action block, or the seq.triggered method?

3

But why create an extra event when you already have an action block

Yes, I agree that the event could be triggered from pass action block as well.
The intent is to trigger the event on sequence match.
The event is actually used to trigger a covergroup.

I am not clear on this.
In my code the event trigger ( → evnt ) would be recognized as a sequence_expression rather than a sequence_match_item , right ?

sequence_match_item uses syntax ::

( sequence_expr {, sequence_match_item } )
4

An event trigger is a procedural statement–it cannot be used in a sequence expression.