Array of constraints challenge

SystemVerilog
, , ,
1

Hi All,

1)fixed array: units[7] = {32’d32,32’d16,32’d26,32’d24,32’d24,32’d24,32’d26}

2)min[7] : min[i] value should be less than units[i]

constraint min_c {
foreach(min[i] min[i] < units[i]);
}
3)limit[7] : limit[i] value should be > min[i] && < units[i]
constraint limit_c{
foreach(limit[i] limit[i] > min[i]);
solve min before limit;
}

Note : No syntax error .random values are not expected values - getting some garbage values.
2 & 3 constraints are not working - plse suggest me,any other way.

Thank you.

2

In reply to gani:
It would help others understand what you are trying to do if you showed the declarations of a variables used and explained what you mean by garbage values. Please show examples of what you are seeing versus what you expect.

Are you using signed or unsigned data types?

3

In reply to dave_59:

generated values.
limit[ 0] = -182822828 min[ 0] = -624238179
limit[ 1] = -172243123 min[ 1] = -1098627795
limit[ 2] = -363088686 min[ 2] = -1889803194
limit[ 3] = -325080374 min[ 3] = -1149947773
limit[ 4] = 292420897 min[ 4] = -877035223
limit[ 5] = 240978027 min[ 5] = -728646870
limit[ 6] = -403211310 min[ 6] = -885775000

int units[7] = {32’d32,32’d16,32’d26,32’d24,32’d24,32’d24,32’d26}
rand int min[7];
rand int limit[7];

Thank you.

4

In reply to gani:

Try using int unsigned or bit [31:0].

5

In reply to gani:

Updated all declarations from int to bit.

bit [31:0]units[7] = {32’d32,32’d16,32’d26,32’d24,32’d24,32’d24,32’d26}
rand bit [31:0] min[7];
rand bit [31:0] limit[7];

Now - min constraint[2] is working as expected ,limit constraint[3] is not working

limit[ 0] = 684002459
limit[ 1] = 1225710199
limit[ 2] = 1624157297
limit[ 3] = 1074405603
limit[ 4] = 1660685905
limit[ 5] = 1447954908
limit[ 6] = 683290020

Thank you.

6

In reply to gani:
How could you expect constraint3 to work if it does not mention units?

What you want is

constraint limit_c{
foreach(limit[i]) limit[i] > min[I] && limit[I] < units[I];
}