Why can’t we use string datatype in SystemVerilog unions? can you please give one example how to use strings in unions?
In reply to Ram130625@:
First of all, unpacked unions are of little practical use in SystemVerilog. As SystemVerilog is primarily a Hardware Description Language, the simulation layout in memory of any datatype is undefined (there is small exception for C compatible data types when arguments are passed through the DPI to C).
The key problem with strings is that they are dynamically sized and no dynamic types are allowed in a union.