Topic	Replies	Views	Activity
Making Testbench Emulation friendly SystemVerilog SV , parameterized-class , Parameterized-classes , Emulation , ParameterizedClass	1	189	June 20, 2024
Parameterised classes UVM UVM , Parameterized-classes	6	1324	January 29, 2019
Cannot extend uvm_event class with different specialization UVM UVM , uvm_event , Overridding-parameterized-class , Parameterized-classes , uvm_event_callback	1	1754	June 1, 2018
I want to use string as a parameter in parameterized class . I could not do it directly like we do for other datatypes. Can we use typecasting or is there any other method to do it? SystemVerilog SystemVerilog , Parameterized-classes	2	1208	May 4, 2018
Parameterized classses UVM UVM , Parameterized-classes	1	1175	August 2, 2017
Parameterizing a class UVM UVM , Parameterized-classes	2	1392	June 10, 2016
Parameterize test base with env type UVM UVM , Parameterized-classes	6	2127	June 7, 2016
VCS Warning for Parameter Class creation ! How to default parameters in parameterized classes? SystemVerilog SystemVerilog , Parameterized-classes , Default-parameters	1	3238	June 2, 2016

Parameterized-classes