Hi,
Could anyone please clarify my doubts ?
Sequence Code :-
reg_model.FW_SPARE0.write(status,32’haaaa_5555);
reg_model.FW_SPARE0.read(status, rdata);
I have following doubts related to RAL model
To check the read data , Do i need to write the Checker logic (to compare the Write data and Read data) ?
Do I need to connect my monitor with the Predictor or reg model mirror value, will the desired value will implicitly get updated ?
In reply to rkg_:
3 Things:
(1) the register read/write have 3 arguments, i.e. status, data and parent. You are missing the parent.
(2) if you want to check what you have written you have to provide the check mechanism by yourself.
(3) You do not show how your RAL integfration/implementation looks like with respect to prediction.
In reply to chr_sue:
Log file :-
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040699ns: reporter [BUS2REG] :: 2 :: addres = f0000684, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040731ns: reporter [BUS2REG] :: 2 :: addres = f0000648, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040763ns: reporter [BUS2REG] :: 2 :: addres = f000013c, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040795ns: reporter [BUS2REG] :: 2 :: addres = f000068c, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040827ns: reporter [BUS2REG] :: 2 :: addres = f00005d0, Data = 0000000000000003, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040859ns: reporter [BUS2REG] :: 2 :: addres = f000045c, Data = 0000001f00000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040891ns: reporter [BUS2REG] :: 2 :: addres = f0000574, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040923ns: reporter [BUS2REG] :: 2 :: addres = f000064c, Data = 0000000000000000, access = RESP_OKAY
Reg Model Msg :
UVM_INFO @ 1040538ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE2=0
UVM_INFO @ 1040570ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FIM2_REF_RD_CLK_PRESCALER_CONFIG=0
UVM_INFO @ 1040602ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_LDTM_OFFSET_1=0
UVM_INFO @ 1040634ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_APB_BRIDGE_BASE=0
UVM_INFO @ 1040666ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_0=0
UVM_INFO @ 1040699ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE3=0
UVM_INFO @ 1040731ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_APB_BRIDGE_OFFSET_1=0
UVM_INFO @ 1040763ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SW_RESET_STATUS=0
UVM_INFO @ 1040795ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.ECO_SPARE_FPGA_REG_POR=0
UVM_INFO @ 1040827ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE_REG1_POR_5=0
UVM_INFO @ 1040859ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_1=0
Predictor Msg :
UVM_INFO /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh(221) @ 1040923ns: uvm_test_top.sve_env.wdc_tb.m_svci_predictor [REG_PREDICT] Observed WRITE transaction to register m_sfr_aon_reg_model.SBS_HIM_OFFSET_1: value='h0 : updated value = 'h0
UVM_INFO /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh(221) @ 1040827ns: uvm_test_top.sve_env.wdc_tb.m_svci_predictor [REG_PREDICT] Observed WRITE transaction to register m_sfr_aon_reg_model.SW_RESET_STATUS: value='h3 : updated value = 'h0
Sequence code :
task body;
if (starting_phase != null)
starting_phase.raise_objection(this);
m_sfr_aon_reg_model.get_registers(sfr_regs);
errors = 0;
sfr_regs.shuffle();
foreach(sfr_regs[i]) begin
ref_data = sfr_regs[i].get_reset();
sfr_regs[i].read(status, data );
if (ref_data != data)begin
`uvm_error("REG_TEST_SEQ:", $sformatf("reset Read error for %s: Expected: %0h Actual: %0h", sfr_regs[i].get_name(), ref_data, data))
errors++;
end
end
endtask
RegModel is always reading 0 means READ DATA is not propagating from predictor (adapter) to REgModel → what to check ?
By Seeing the above log file can we conclude what can be wrong in my ENV?
In reply to rkg_:
You are still missing the 3rd argument in the read command. It has to be
sfr_regs[i].read(status, data, this);
Some registers returning a read value different to 0.
And you do not show the access policy of the registers. Some of them might be RO or WO.
Dou you have volatile registers?
In reply to chr_sue:
sfr_regs[i].read(status, data, this);
By adding this , i am seeing the same ( did not see any change in my log ) .
few are RO registers and most are RW only.
None of registers are returning a read different to 0.
class ral_reg_sfr_top_SW_RESET_STATUS extends uvm_reg;
rand uvm_reg_field DSG0_RESET_STATUS;
rand uvm_reg_field DSG1_RESET_STATUS;
function new(string name = "sfr_top_SW_RESET_STATUS");
super.new(name, 8,build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.DSG0_RESET_STATUS = uvm_reg_field::type_id::create("DSG0_RESET_STATUS",,get_full_name());
this.DSG0_RESET_STATUS.configure(this, 1, 0, "RO", 1, 1'h1, 1, 0, 0);
this.DSG1_RESET_STATUS = uvm_reg_field::type_id::create("DSG1_RESET_STATUS",,get_full_name());
this.DSG1_RESET_STATUS.configure(this, 1, 1, "RO", 1, 1'h1, 1, 0, 0);
endfunction: build
class ral_reg_sfr_top_SBS_HIM_OFFSET_0 extends uvm_reg;
rand uvm_reg_field SEL_POL;
rand uvm_reg_field MASK;
rand uvm_reg_field ADDR;
function new(string name = "sfr_top_SBS_HIM_OFFSET_0");
super.new(name, 32,build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.SEL_POL = uvm_reg_field::type_id::create("SEL_POL",,get_full_name());
this.SEL_POL.configure(this, 1, 0, "RW", 0, 1'h0, 1, 0, 0);
this.MASK = uvm_reg_field::type_id::create("MASK",,get_full_name());
this.MASK.configure(this, 13, 3, "RW", 0, 13'h0, 1, 0, 0);
this.ADDR = uvm_reg_field::type_id::create("ADDR",,get_full_name());
this.ADDR.configure(this, 13, 19, "RW", 0, 13'h0, 1, 0, 1);
endfunction: build
Does access policy and Volatile will impact the result ? Since i am checking the POR value of all registers just after reset DE assertion.
Problem here is none of the registers are different then 0.
Eq:-
UVM_INFO @ 1040859ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_1=0
In reply to rkg_:
You cannot modify a RO register using the write command. It is doing nothing but returns UVM_IS_OK.
If you want to modify such a register you have to use the backdoor access (poke is the best command).
If you have a volatile register this content can be modified directly from the DUT. If this happens between the write and the read command you’ll see a different value. Most volatile registers are RO.
You are right all read values are 0. I was looking to the write command (bus2reg) report data.
I do not understand your create command for the field. You are using
this.ADDR = uvm_reg_field::type_id::create("ADDR",,get_full_name());
But it should be simply
ADDR = uvm_reg_field::type_id::create("ADDR");
In reply to chr_sue:
This is generated by RALGEN tool .
this.ADDR = uvm_reg_field::type_id::create(“ADDR”,get_full_name());
I am sorry , I am not sure that i got any hint from your previous comment ? Am i missing anything in my ENV ? why I am getting data (actual)= 0 for all registers for reset and xpected data is coming correct
1036171ns: uvm_test_top.sve_env.wdc_tb.svci_masters[0].svci_master_cmd_sequencer@@svci_ral_reg_rw_seq [REG_TEST_SEQ:] reset Read error for FLASH0_CTRL_SELF_TEST: Expected: f6 Actual: 0
In reply to rkg_:
You have RO registers. RO registers cannot be written by the write command in the FRONTDOOR mode. Most RO registers are volatile registers which can be modified directly by the DUT (internally). If you want to modify them from your testbench you have to use the BACKDOOR access. A BACKDOOR write is the poke command. You can use it.
In reply to chr_sue:
I believe, I am not writing anything into my DUT.
I have written sequence to check the POR value of all registers.
task body;
if (starting_phase != null)
starting_phase.raise_objection(this);
m_sfr_aon_reg_model.get_registers(sfr_regs);
errors = 0;
sfr_regs.shuffle();
foreach(sfr_regs[i]) begin
ref_data = sfr_regs[i].get_reset();
sfr_regs[i].read(status, data );
if (ref_data != data)begin
`uvm_error("REG_TEST_SEQ:", $sformatf("reset Read error for %s: Expected: %0h Actual: %0h", sfr_regs[i].get_name(), ref_data, data))
errors++;
end
end
In reply to rkg_:
This was my misunderstanding. Then you should read back the reset values.
The bus2reg shows 2 data which are not 0.
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040827ns: reporter [BUS2REG] :: 2 :: addres = f00005d0, Data = 0000000000000003, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040859ns: reporter [BUS2REG] :: 2 :: addres = f000045c, Data = 0000001f00000000, access = RESP_OKAY.
It dpes not display the register name but the address.
And you still have not the 3rd argument in your read command:
sfr_regs[i].read(status, data, this );
In reply to chr_sue:
I will correct it
sfr_regs[i].read(status, data, this );
Correct, I am getting value value at bus2reg but same is not reflecting at REGMODEL (means data is 0 always )
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040859ns: reporter [BUS2REG] :: 2 :: addres = f000045c, Data = 0000001f00000000, access = RESP_OKAY.
RegModel :
UVM_INFO @ 1040763ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SW_RESET_STATUS=0
UVM_INFO @ 1040795ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.ECO_SPARE_FPGA_REG_POR=0
UVM_INFO @ 1040827ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE_REG1_POR_5=0
UVM_INFO @ 1040859ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_1=0
Means something is broken from bus2reg to remogmodel. thus test is failing
if (ref_data != data).
So is their any hint to debug what is the wrong in my ENV ???
In reply to rkg_:
bus2reg is not storing anything. Did you also the registers in the DUT?
In reply to chr_sue:
In waveform, I can see DUT registers value .
Did you also the registers in the DUT? ??? i did not understand
In reply to rkg_:
Did you also reset your DUT registers and not only the registers in the TB.
Could you share your code privately with me? Currently it is guessing what I’m doing.
This is not a good approach.
You can send me your data to
christoph@christoph-suehnel.de.
In reply to chr_sue:
Yes i have reset the DUT after i initialized the SOC then i am checking the POR value of all registers.
Hi, Did you guys able to solve this issue. I am facing something similar