In reply to chr_sue:
sfr_regs[i].read(status, data, this);
By adding this , i am seeing the same ( did not see any change in my log ) .
few are RO registers and most are RW only.
None of registers are returning a read different to 0.
class ral_reg_sfr_top_SW_RESET_STATUS extends uvm_reg;
rand uvm_reg_field DSG0_RESET_STATUS;
rand uvm_reg_field DSG1_RESET_STATUS;
function new(string name = "sfr_top_SW_RESET_STATUS");
super.new(name, 8,build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.DSG0_RESET_STATUS = uvm_reg_field::type_id::create("DSG0_RESET_STATUS",,get_full_name());
this.DSG0_RESET_STATUS.configure(this, 1, 0, "RO", 1, 1'h1, 1, 0, 0);
this.DSG1_RESET_STATUS = uvm_reg_field::type_id::create("DSG1_RESET_STATUS",,get_full_name());
this.DSG1_RESET_STATUS.configure(this, 1, 1, "RO", 1, 1'h1, 1, 0, 0);
endfunction: build
class ral_reg_sfr_top_SBS_HIM_OFFSET_0 extends uvm_reg;
rand uvm_reg_field SEL_POL;
rand uvm_reg_field MASK;
rand uvm_reg_field ADDR;
function new(string name = "sfr_top_SBS_HIM_OFFSET_0");
super.new(name, 32,build_coverage(UVM_NO_COVERAGE));
endfunction: new
virtual function void build();
this.SEL_POL = uvm_reg_field::type_id::create("SEL_POL",,get_full_name());
this.SEL_POL.configure(this, 1, 0, "RW", 0, 1'h0, 1, 0, 0);
this.MASK = uvm_reg_field::type_id::create("MASK",,get_full_name());
this.MASK.configure(this, 13, 3, "RW", 0, 13'h0, 1, 0, 0);
this.ADDR = uvm_reg_field::type_id::create("ADDR",,get_full_name());
this.ADDR.configure(this, 13, 19, "RW", 0, 13'h0, 1, 0, 1);
endfunction: build
Does access policy and Volatile will impact the result ? Since i am checking the POR value of all registers just after reset DE assertion.
Problem here is none of the registers are different then 0.
Eq:-
UVM_INFO @ 1040859ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_1=0