RAL Model Doubts

In reply to chr_sue:

This is generated by RALGEN tool .
this.ADDR = uvm_reg_field::type_id::create(“ADDR”,get_full_name());

I am sorry , I am not sure that i got any hint from your previous comment ? Am i missing anything in my ENV ? why I am getting data (actual)= 0 for all registers for reset and xpected data is coming correct

1036171ns: uvm_test_top.sve_env.wdc_tb.svci_masters[0].svci_master_cmd_sequencer@@svci_ral_reg_rw_seq [REG_TEST_SEQ:] reset Read error for FLASH0_CTRL_SELF_TEST: Expected: f6 Actual: 0