In reply to chr_sue:
Log file :-
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040699ns: reporter [BUS2REG] :: 2 :: addres = f0000684, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040731ns: reporter [BUS2REG] :: 2 :: addres = f0000648, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040763ns: reporter [BUS2REG] :: 2 :: addres = f000013c, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040795ns: reporter [BUS2REG] :: 2 :: addres = f000068c, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040827ns: reporter [BUS2REG] :: 2 :: addres = f00005d0, Data = 0000000000000003, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040859ns: reporter [BUS2REG] :: 2 :: addres = f000045c, Data = 0000001f00000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040891ns: reporter [BUS2REG] :: 2 :: addres = f0000574, Data = 0000000000000000, access = RESP_OKAY
UVM_INFO /home/SwiftProMp16_B0/users/rupeshg/swiftB_B0_r3_wy/11_top/verification/testbench/mihir_uvm_sv_tb/wdc_tb/tbcs/wdc_apb/sv/wdc_svci_adapter.sv(105) @ 1040923ns: reporter [BUS2REG] :: 2 :: addres = f000064c, Data = 0000000000000000, access = RESP_OKAY
Reg Model Msg :
UVM_INFO @ 1040538ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE2=0
UVM_INFO @ 1040570ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FIM2_REF_RD_CLK_PRESCALER_CONFIG=0
UVM_INFO @ 1040602ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_LDTM_OFFSET_1=0
UVM_INFO @ 1040634ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_APB_BRIDGE_BASE=0
UVM_INFO @ 1040666ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_0=0
UVM_INFO @ 1040699ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE3=0
UVM_INFO @ 1040731ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_APB_BRIDGE_OFFSET_1=0
UVM_INFO @ 1040763ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SW_RESET_STATUS=0
UVM_INFO @ 1040795ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.ECO_SPARE_FPGA_REG_POR=0
UVM_INFO @ 1040827ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.FW_SPARE_REG1_POR_5=0
UVM_INFO @ 1040859ns: reporter [RegModel] Read register via map m_sfr_aon_reg_model.uvm_reg_map: m_sfr_aon_reg_model.SBS_HIM_OFFSET_1=0
Predictor Msg :
UVM_INFO /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh(221) @ 1040923ns: uvm_test_top.sve_env.wdc_tb.m_svci_predictor [REG_PREDICT] Observed WRITE transaction to register m_sfr_aon_reg_model.SBS_HIM_OFFSET_1: value='h0 : updated value = 'h0
UVM_INFO /pga/cadence/xcelium/19.09.003/tools/methodology/UVM/CDNS-1.1d/sv/src/reg/uvm_reg_predictor.svh(221) @ 1040827ns: uvm_test_top.sve_env.wdc_tb.m_svci_predictor [REG_PREDICT] Observed WRITE transaction to register m_sfr_aon_reg_model.SW_RESET_STATUS: value='h3 : updated value = 'h0
Sequence code :
task body;
if (starting_phase != null)
starting_phase.raise_objection(this);
m_sfr_aon_reg_model.get_registers(sfr_regs);
errors = 0;
sfr_regs.shuffle();
foreach(sfr_regs[i]) begin
ref_data = sfr_regs[i].get_reset();
sfr_regs[i].read(status, data );
if (ref_data != data)begin
`uvm_error("REG_TEST_SEQ:", $sformatf("reset Read error for %s: Expected: %0h Actual: %0h", sfr_regs[i].get_name(), ref_data, data))
errors++;
end
end
endtask
RegModel is always reading 0 means READ DATA is not propagating from predictor (adapter) to REgModel → what to check ?
By Seeing the above log file can we conclude what can be wrong in my ENV?