RAL Model Doubts

UVM
,
9

In reply to chr_sue:

I believe, I am not writing anything into my DUT.

I have written sequence to check the POR value of all registers.

 task body;  
 
    if (starting_phase != null)
      starting_phase.raise_objection(this);
 
  m_sfr_aon_reg_model.get_registers(sfr_regs);
 
    errors = 0;
 
    sfr_regs.shuffle();
    foreach(sfr_regs[i]) begin
      ref_data = sfr_regs[i].get_reset();
      sfr_regs[i].read(status, data );
      if (ref_data != data)begin
        `uvm_error("REG_TEST_SEQ:", $sformatf("reset Read error for %s: Expected: %0h Actual: %0h", sfr_regs[i].get_name(), ref_data, data))
                   errors++;
                   end
end