Issue with RAL Coverage bins creation

Hi Dave, chr_sue,

We are working on RAL Coverage. We used Questa Regassist Tool to create UVM reg Model along with Covergroups creation.

We are using Questsim tool to run our simulations.

Ex: If we have two fields in a register, cover group is created like mentioned below:

Questasim Tool is creating 2^8 bins for the first field and 2^16 bins for the second field.

In the same way, it is creating 2^(width) bins for all fields for all the registers.

But we are doing bit-bash tests only now ie., we are sending only all F’s, A’s, 0’s, 5’s, random data to all registers.

As shown in the below screenshots, 255 bins are getting created for my first field. But I’m not interested in creating those many bins for all fields for all registers.


Is there any way to stop creating these many bins as per the width of that respective field?
As these many bins are creating, our RAL coverage % is very less, even though the test is PASSED.

It would be helpful if it creates a scalar bin or limited number of bins for every field.
Could you please suggest on this.

A coverpoint without an explicit bins generates a maximum of 64 bins. This may be controlled by the auto_bin_max option in the declaration of the covergroup. The 64 bins get evenly distributed amongst the possible values of the coverpoint expression. If you need some other way of limiting the bins create, you need to write that yourself.

ok Dave,

is there any approach to generate UVM_CVR_REG_BITS related coverage with Questa Regassist Tool?
By default, it is creating UVM_CVR_FIELD_VALS related coverage only.

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