UVM Adapter for Pipelined protocols like AHB, AXI etc


I have been running this uvm_reg_hw_reset_seq sequence for the AHB protocol. My UVM Adapter looks like:

class ahb_adapter extends uvm_reg_adapter; 
  function new(string name = "ahb_adapter"); 
    //this.provides_responses = 1; // This is set if the driver sends the responses. 
  virtual function uvm_sequence_item reg2bus (const ref uvm_reg_bus_op rw);
    ahb_transaction bus_item = ahb_transaction::type_id::create("bus_item");
    bus_item.data = new[1]; 
    bus_item.busy = new[1]; 
    bus_item.addr = rw.addr;
    bus_item.data[0] = rw.data;
    bus_item.kind = (rw.kind == UVM_READ) ? READ: WRITE;
    // More AHB specific items to transfer over the AHB Agent
    bus_item.size   = WORD;
    bus_item.wrap   = 0;
    bus_item.htrans = NONSEQ;
    bus_item.hburst = SINGLE; 
    bus_item.busy[0] = 0; 

    //`uvm_info(get_type_name, $sformatf("reg2bus: addr = %0h, data = %0h, rd_or_wr = %0h", bus_item.addr, bus_item.data[0], bus_item.kind), UVM_LOW);
    return bus_item;
  virtual function void bus2reg (uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
    ahb_transaction bus_pkt;
    if(!$cast(bus_pkt, bus_item))
      `uvm_fatal(get_type_name(), "Failed to cast bus_item transaction")

    rw.addr = bus_pkt.addr;
    rw.kind = (bus_pkt.kind == READ) ? UVM_READ: UVM_WRITE;
    rw.data = bus_pkt.data[0];
    //`uvm_info(get_type_name, $sformatf("bus2reg: addr = %0h, data = %0h, rd_or_wr = %0h", bus_pkt.addr, bus_pkt.data[0], bus_pkt.kind), UVM_LOW);

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the uvm_reg_hw_reset_seq sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the uvm_reg_hw_reset_seq. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.