I have a question about the read() function of register abstraction layer (RAL) of UVM.
From my understanding, when a read() is performed, BOTH the mirror and desired registers are updated by the actual DUT value. I understand why the mirrored value is updated, but why would the desired register be updated?
I think this causes an issue: If I have a case where a DUT bug causes an incorrect register value to be returned on a read. The read mismatches my desired register value and an error is generated by the testbench as expected. However, if I do a second read, no error is detected because the desired register model was updated during the previous read and now matches the DUT value. It also seems like I could even have a race condition where the desired is update before my comparison is done and not see the mismatch.
Can you provide a brief rationale for why the desired register is updated to the dut value? I would expect only the mirrored value to be updated.
Thanks Dave, I think knowing about the “update” functionality helped provide some rationale for it anyway.
I has been thinking the desired value was my ‘predicted’ or expected value, but perhaps that belongs somewhere else in a predictor model? This is my first time using RAL so it’s a little new to me.
Thanks (as always) for your replies and explanations,
Brian
“The read mismatches my desired register value and an error is generated by the testbench as expected. However, if I do a second read, no error is detected because the desired register model was updated during the previous read and now matches the DUT value. It also seems like I could even have a race condition where the desired is update before my comparison is done and not see the mismatch.”
I am little bit confused with these statements. Can you please mention through some pseudo code, how would you get error in first statement, how you won’t get in second statement and how race condition could happen. The rational of mirror and desired value update we understood from Dave’s link. But just thinking to catch DUT bug’s in the scenario you explained.
I think there are volatile registers which value can change between access.
So if you assume that the read value is always correct, then you need to update the desire value.
If it is not volatile register, I also don’t see the problem of modifying the desired value after read. Because the first error appearance already told you that there is dut bug which needs to be solved.
And since read modified your mirrored value, desired value needs to be updated too because if not then your desired value will be different from mirror value. That means update() will do bus write even you didn’t set any register. The rationale is that update() should only do bus write when the test wants to set registers to value different from the current dut value.