Mixed packed and unpacked array

SystemVerilog
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1

Hi,

i didnt understand the below declaration of arrays. can any one explain me the declaration of below array and how to assign values to the below arrays? how to do part select with these arrays?

  1. reg [7:0] [0:4] mem2 [0:1];

  2. reg [7:0] [0:4] mem3 [0:1] [0:1];

Thanks in advance,

3

hi nag_sv

while dealing with memory we consider like this
[WIDTH] mem [DEPTH]; // left side is width and right side is depth.
we can make slices the width and depth.
we can take entire slice or one bit of slice.
To access the memory of width first we require in which slice our data is after that which bit.
i.e reg [7:0] [0:4] mem2 [0:1];
in this example [bit_position][slice_position]mem [depth];
our memory is having 5 ([0:4]) slices each having 8 bits ([7:0]).

our memory 76543210 | 76543210 | 76543210 | 76543210 |76543210
slice 0 | 1 | 2 | 3 | 4

like that there (0,1) depths are there.

to access the memory location in which depth it is after that which slice
it is after that what is the bit position.
i.e [3][1]mem[0] which means in depth of 0 in slice 1 3rd bit.

Thanks
Gunnesh

4

Hi inkulagunnesh,

Could you kindly site the source of this information please.
as of my knowledge for reg [7:0][0:4] mem [0:1] .
ie [slice_position][bit_position] mem [depth].

There are 8 , 5 bit register with the depth of 2. So total there are 16, 5 bit registers in which the first 8, 5 bit register are accessed by 0 and the next 8 are accessed by 1.

                      0                   1               2              3                4                5               6
Depth - 0 | 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4|
Depth - 1 | 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4| 0 1 2 3 4|

In order to access the values
a[0][0][0] → In depth 0 , 0th subfield, 0th bit.
a[1][6][6] → in depth 1, 6th subfield, 6th bit.
Source : Maven Silicon

Thanks
MVS Abhiram

5
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