How to implement clock in program block?
Do not use program blocks. It actually contribute to race conditions if you have clocking blocks triggered from events in the reactive region.
Hello Akshat,
You cannot use an always procedural block inside a program; it cannot be placed inside classes or other System Verilog procedural blocks. Instead, you can use a forever loop to achieve the same effect, but as @dave_59 suggests, it actually contributes to race conditions.
You can approach the module with a clocking block to give input and output skew values.
Thanks