Non-compute-intensive way to add an asynchronous delay to a transaction

UVM
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1

Hi community,

The idea is to have one of the sequence parameters be an asynchronous delay in picoseconds between when the sequence is started, and when one of its signals is driven to the port.

I implemented a synchronous version of the delay succesfully, where the driver triggers at each clock cycle and checks the number of elapsed cycles since receiving the transaction to know if it can drive the port signals yet

Doing the same for an asynchronous delay would mean using a driver loop that triggers every picosecond, which quickly makes simulation runtime explode for larger designs.

Using SystemVerilog

Suggestions on how to proceed?

2

You should realize the sequence/sequencer does not know anything about timing and clock cycles. Any timing has to be implemented in the driver. If you have an RTL design the timing does not matter. Timing is only relevant for a gate level model. If you do not want to synchronize on the clock edge in the driver you can have a timing delay as a data member in the sequnce. In the driver you can synchronize on this delay after the clock edge.