Macro to read register fields using RAL

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1

Hi, here is my error. I have 3 regmodels in my testbench. so I wanted a write a macro, for read n write reg using RAL.

`define MC0_READ_REG (field, field_value) \
        uvm_reg_field register; \
        register = mc0_regmodel.get_field_by_name(`"field`"); \
        register.mirror(status); \
        field_value = register.get();
 


 task read_registers();
    	`uvm_info(get_type_name(),$sformatf(" read coverpoints "),UVM_LOW)
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
    endtask : read_registers.

This is how I defined macro and using. But I’M getting syntactical errors below. I tried all the variations but it didn’t work.
Errors:

xmvlog: *E,NOTSTT (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|20): expecting a statement [9(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                    |
xmvlog: *E,MISEXX (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|20): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                    |
xmvlog: *E,MISEXX (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|20): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                    |
xmvlog: *E,MISEXX (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|20): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                     |
xmvlog: *E,NOTSTT (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|21): expecting a statement [9(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                                              |
xmvlog: *E,MISEXX (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|46): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
        `MC0_READ_REG(AXI0_FIXED_PORT_PRIORITY,axi_fixed_port_priority);
                                                                      |
xmvlog: *E,MISEXX (/nsfs/devarsim2/greddy/SS/ddrss_coverage/verif/sim/../../verif/tb/uvm/rel/top/rel_ddrss_top_coverage.sv,134|70): expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].

What could be the reason?
Thanks in advance.

2

Your macro contains a variable declaration register. Variable declarations are not allowed in the middle of a procedural block. Put begin/end around the body of your macro. This also keeps the declaration local to the block so you can use the macro several times within the same procedural block of code.