Hi All,
I’m writing an assertion to check ‘sig’ does change before or at end of simulation
Here is my attempt :: X_EDA
There are 2 possible scenarios
(1) Case1 : Using +define+C1 where simulation ends at T:47 units
(2) Case2 : Absence of +define+C1 where simulation ends at T:45 units i.e simulation ends at exactly the last clock
For Case1, two tools give output as
T:45 Pass
T:47 Pass via final
Whereas 2 tools execute the pass/fail action block at T:47 for the SVA which is incorrect
The final block executes at T:47 and would sample the NBA updated value at T:45
For Case2 as $finish() executes in Active region of T:45 the SVA isn’t evaluated in Observed region.
The SVA fails at T:45 due to strong operator ( this is as per expectations )
I have a few questions on the final block execution at T:45 for Case2 ::
(Q1) Does the LRM define order of execution between strong & final block ? ( both would execute at T:45 )
(Q2) Does the final block use Sampled value ( i.e pre-poned value ) of ‘sig’ or the NBA updated value ?
(Q3) If I were to call subroutine ‘SIG()’ within the final block. In which region would the subroutine ‘SIG’ be called ? Would the final block use the NBA updated value of ‘1’ ?
final begin
if( $changed(SIG(),@(posedge clk)) ) $display("T:%2t Pass via final",$time);
else $display("T:%2t Fails via final",$time);
end