Topics tagged Clock-domain-crossing

Topic	Replies	Views	Activity
SVA and clock domain crossing SystemVerilog SystemVerilog , SVA , SVA-Assertion , Clock-domain-crossing , CDC	9	5806	April 18, 2025
In FIFO for writing data into FIFO WE use one clock and from reading the data from FIFO we are using different clock and FIFO is just 1 word deep SystemVerilog SystemVerilog , fifo , Clock-domain-crossing , asynchronous , data-flow-synchronization	3	1010	December 29, 2022
Cover() failed for asynchronous fifo SystemVerilog SystemVerilog , fifo , Clock-domain-crossing , asynchronous , assertion-coverage	6	2513	February 6, 2019