In FIFO for writing data into FIFO WE use one clock and from reading the data from FIFO we are using different clock and FIFO is just 1 word deep

SystemVerilog
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1

Hi,

I had a doubt if we use two clocks for transmitting the data in FIFO and read clock is 5x times slower then the write clock or vice versa what actual happens and how FIFO will work if we are using one clock frequency for writing and different clock frequency for the read and how write data and read will synchronize . can anyone please explain me briefly about this scenario and if you explain with an example it will be helpful for me.

Thanks in advance
Harshavardhan

2

Hi Dave,

My question is not regarding UVM sorry I mistakenly put that I am asking question regarding to the module design of FIFO. In FIFO design they used one clock frequency to write data into FIFO and one clock frequency to read data from FIFO. Please explain me how synchronization happens between read and write.

Thanks in advance
Harshavardhan

3

In reply to Harsha vardhan:

there is no problem if the read/write address(pointer) is encoded with gray code, even if there is big frequency difference cross the two clock domain, because every time the write/read pointer is synchronized to another domain, there is only one bit may change.

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In reply to Harsha vardhan:

Then what you are asking for is not really a FIFO, it is a “fast to slow clock domain crossing synchronizer”. I would do a search for the quoted text.