In FIFO for writing data into FIFO WE use one clock and from reading the data from FIFO we are using different clock and FIFO is just 1 word deep

SystemVerilog
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In reply to Harsha vardhan:

there is no problem if the read/write address(pointer) is encoded with gray code, even if there is big frequency difference cross the two clock domain, because every time the write/read pointer is synchronized to another domain, there is only one bit may change.