Topics tagged DUT-parameters

Topic	Replies	Views	Activity
Passing TB/RTL parameters to sequences UVM UVM , DUT-parameters , ParameterizedClass	3	1089	November 14, 2020
Variable in Hierarchical access SystemVerilog SystemVerilog , hierarchy , macros , DUT-parameters	2	2433	September 13, 2019
Access internal module signals via bind if internal signals depends on generate block SystemVerilog SystemVerilog , bind , binding-in-SV , DUT-parameters	0	2174	October 21, 2018
Race condition setting config from testbench parameter UVM UVM , testbench , uvm_config_db , DUT-parameters	3	2283	August 1, 2016
Changing the DUT parameters UVM UVM , DUT-parameters	3	4746	May 5, 2016

Passing TB/RTL parameters to sequences

UVM , DUT-parameters , ParameterizedClass

3

1089

November 14, 2020

Variable in Hierarchical access

SystemVerilog , hierarchy , macros , DUT-parameters

2

2433

September 13, 2019

SystemVerilog , bind , binding-in-SV , DUT-parameters

0

2174

October 21, 2018

Race condition setting config from testbench parameter

UVM , testbench , uvm_config_db , DUT-parameters

3

2283

August 1, 2016

Changing the DUT parameters

UVM , DUT-parameters

3

4746

May 5, 2016