Hello ,
I want to change the DUT parameters through my tests/class. Is it possible ?
Regards,
In reply to uvm_user123:
If by “parameter” you mean a Verilog module parameter or a VHDL generic, it is not possible. Parameters are compile time constants and their values must be fixed before any class ever gets constructed.
What some people do is put their parameters in a common package that is used by both the DUT and testbench. You can create different version of the package for each combination of parameter sets that you need. You can even use SystemVerilog random constraints to write the package with randomized sets of parameter values.
In reply to dave_59:
Dave_59,
Is there an example to show the random constraints for a package?
Also, can the parameters for Classes (agents, driver, monitors) which typically define the width of a logic signal (bus) be changed from a test case? And how? Can a configuration class hold these values and then be used to instantiate Agent, Drivers and monitors?
Thanks!
In reply to gopal_susarla:
https://verificationacademy.com/forums/ovm/randomizing-module-parameters
The same problem exists for parameters for classes - you cannot change them at runtime.
So you need to chose carefully which things in your class need to be parameterized. You don’t always need to size variables in your testbench to match the size of signals in your DUT. You just need to make them large enough to hold whatever size the signal could ever be.