In reply to uvm_user123:
If by “parameter” you mean a Verilog module parameter or a VHDL generic, it is not possible. Parameters are compile time constants and their values must be fixed before any class ever gets constructed.
What some people do is put their parameters in a common package that is used by both the DUT and testbench. You can create different version of the package for each combination of parameter sets that you need. You can even use SystemVerilog random constraints to write the package with randomized sets of parameter values.