Randomizing Module Parameters

I need to verify a module that has several parameters using OVM, and make sure that all values for each parameter is verified.
However, the total combinations of all of them takes too long to simulate, so I want to randomize them at the start of each simulation seed.
Is there a way to randomize these parameters? I am not sure if this issue relates with OVM in the instantiation of the module, or if it is more with the command line of the simulator. I am using Questasim.

You can’t randomize SV parameter values in one pass. You can create a separate model to output parameter values in the form of a package, or as values for command line options for a second pass that modifies the parameters for the module in your design. In any case, you could create a covergroup that samples the values of these parameters over the course of your regression suite.

Dave

Hi Dave,

You can’t randomize SV parameter values in one pass. You can create a separate model to output parameter values in the form of a package

I did not understand how we can do this practically. Can you explain elaborately.

I don’t have the time for an elaborate example but this should help get the point across;

module top_pass1;
  class A;
  rand int unsigned N_SLAVES;
  rand int unsigned N_MASTERS;
  constraint C { N_SLAVES < 10; N_MASTERS < N_SLAVES;}
  function void printPackage;
      int f = $fopen("my_package.sv");
      $fdisplay(f, "package my_package;");
      $fdisplay(f, "  parameter N_SLAVES = %0d;",N_SLAVES);
      $fdisplay(f, "  parameter N_MASTERS = %0d;",N_MASTERS);
      $fdisplay(f, "endpackage");
   endfunction
   endclass

A a;
initial begin
    a = new();
    a.randomize();
    a.printPackage();
end
endmodule

This should produce something like

package my_package;
  parameter N_SLAVES = 7;
  parameter N_MASTERS = 2;
endpackage

Then the second pass you would compile my_package along with the rest of your design

module top_of_your_design;
 
 for (int i=0;i < my_package::N_SLAVES; i++) begin : SLAVES
  slave_module s(...);
 end
 for (int i=0;i < my_package::N_MASTERS; i++) begin : MASTERS
  master_module s(...);
 end
endmodule

Dave Rich

Hi Dave,

That was an innovative solution. While I feel that it can nicely alter an verification environment(class-based), I feel that it fells short of configuring a DUT with many parameters.

For example

module top;

my_DUT #(.ADDR_WIDTH (8)) myDUTobj;


endmodule

So here, IMHO, we need a script taking care of all different parameters going into the DUT. Please let me know, if what I am thinking is incorrect.

For Questasim the option to pass parameters is -G<param_name>=<param_value>
NC, the command is defparam.

-Sharat

You can make the output of the first pass output whatever you need; command line options, Tcl script commands, defparam overrides.

I just wish the Verilog trainers out there would teach design engineers proper programming practices: never hardcode constants directly in your source - create symbols that can be globally modified in a central location.

my_DUT #(.ADDR_WIDTH (my_DUT_pkg::DUT_ADDR_WIDTH)) myDUTobj;

Thank you Dave.